1. Field of the Invention
The present invention relates to the field of data transfer. More particularly, the present invention relates to a circuit and method for enhancing performance of an address translation unit ("ATU") by using system software and minimal circuitry to segregate its addressable memory into locked and unlocked regions.
2. Description of Art Related to the Invention
For over a decade, a number of system architectures have been developed with input/output ("I/O") devices accessing main memory through direct virtual memory accesses DVMA using virtual addresses, instead of direct memory accesses ("DMAs") using physical addresses. One advantage associated with DVMA systems has been the simplification of data accesses by the I/O devices. For example, I/O devices accessing memory through DMAs ("DMA I/O devices") must be controlled to "scatter" (or allocate) data to a number of potentially discontiguous physical pages as well as to "gather" data. Gathering data that exceeds one page in length is normally accomplished by accessing a group of potentially discontiguous physical pages. In contrast, I/O devices that access main memory through DVMAs ("DVMA I/O devices") do not require such control because data accesses are made through contiguous virtual pages.
Although the DVMA systems have simplified this "scatter-gather" problem, these systems require the virtual addresses issued by the DVMA I/O devices to be translated into physical addresses before data can be accessed from main memory. As shown in FIG. 1, a conventional DVMA system 100 utilizes an I/O Memory Management Unit "I/O MMU" 110, sometimes referred to as an I/O Translation Lookahead Buffer, to translate virtual addresses to physical addresses utilized by main memory 120. As shown, the I/O MMU 110 is implemented within a bridge element 130 that couples an I/O bus 140 and a system bus 150.
Typically, the I/O MMU 110 is often configured to contain a limited number "r" thereof address translations of internal memory to increase system performance with minimal additional costs. Each of these address translations is assigned to a designated entry of internal memory. For example, the internal memory may include 16 fully-associative entries. The entries may be uniquely designed through tag bit(s) as an "unlocked" entry or a "locked" entry. A locked entry contains contents considered to be "generally static" because these contents are modified less often than unlocked entries. Thus, the contents of the unlocked entry is considered to be "generally dynamic" because the contents are modified with greater frequency than other entries in I/O MMU. A search engine is implemented in the I/O MMU 110 to check the tag bits during entry replacement.
However, the conventional entry locking mechanism imposes a number of disadvantages on current systems. One disadvantage associated with the conventional lock entry mechanism relates to increased costs associated with increased memory requirements to accommodate tag bits, develop search engine circuitry and use of limited I/O MMU space. Moreover, there are performance costs due to the presence of long lookup times.
With the emergence of multi-media communications, networks are now being required to support multiple data types. As a result, network manufacturers are tending to concentrate their efforts toward asynchronous transfer mode ("ATM") networks. In ATM networks, a large number of virtual channels, perhaps hundreds, can be in operation simultaneously. Hence, if the DVMA system 100 is configured to support an ATM network coupled to I/O network interface logic 170, it would experience significant performance degradation caused by excessive fetching of address translations from main memory.
To substantially avoid performance degradation, an address translation unit ("ATU") may be implemented within a Network Interface Circuit ("NIC") coupled to the I/O bus. The NIC would be used to interconnect the ATM network environment to the DVMA system. Thus, the I/O MMU may be bypassed by the ATU, placing a physical address on the I/O bus instead of a virtual address. To accomplish this task, the ATU would contain a set of modifiable virtual-to-physical address translations, and thereby would experience the same disadvantages experienced by the I/O MMU upon adopting the conventional lock entry mechanism utilizing tag bits.
Hence, it would be advantageous to develop an entry locking mechanism that avoids the use of tag bits, but rather relies on system software to allocate which portions of internal memory within the ATU are generally static and which portions are dynamic.